555 Timer Astable Oscillator Circuit timing is set by two resistors and a capacitor. Enter R1, R2 and C for frequency and duty cycle, or work out R1 and R2 from a target frequency.
R1 runs from +V to pin 7, R2 from pin 7 to pins 6 and 2, and C from those pins to ground.
Chip, Supply and Parts
Frequency With Other Capacitors
| Capacitor | Frequency | Period |
|---|---|---|
| 100 pF | 102.5 kHz | 9.753 µs |
| 1 nF | 10.25 kHz | 97.53 µs |
| 10 nF | 1.025 kHz | 975.3 µs |
| 100 nF | 102.5 Hz | 9.753 ms |
| 1 µF | 10.25 Hz | 97.53 ms |
| 10 µF | 1.025 Hz | 975.3 ms |
| 100 µF | 0.103 Hz | 9.753 s |
| 1000 µF | 10.25 mHz | 1.625 min |
Potentiometer Sweep on R2
| Pot Turned | R2 Total | Frequency | Duty |
|---|---|---|---|
| 0% | 68 kΩ | 1.025 Hz | 51.7% |
| 25% | 93 kΩ | 0.757 Hz | 51.2% |
| 50% | 118 kΩ | 0.599 Hz | 51.0% |
| 75% | 143 kΩ | 0.496 Hz | 50.8% |
| 100% | 168 kΩ | 0.423 Hz | 50.7% |
Wiring Diagram With Pin Numbers
How a 555 Timer Astable Oscillator Circuit Runs
A 555 timer astable oscillator circuit has no stable state, so pin 3 keeps switching between high and low on its own. Two resistors and one capacitor set the timing. R1 runs from the supply to pin 7, R2 runs from pin 7 to pins 6 and 2, and C runs from those pins to ground.
C charges through R1 and R2 while the output is high. When C reaches two thirds of the supply, pin 7 switches to ground and C drains through R2 alone. At one third of the supply the output goes high again. The Texas Instruments NE555 data sheet gives the timing equations for both halves of the cycle.
Those two trip points act like the upper and lower thresholds worked out in the Schmitt Trigger Calculator. Both scale with the supply, so the standard 555 timer oscillator circuit holds its frequency when the supply moves. TI lists a typical astable supply sensitivity of 0.3% per volt.
555 Timer Astable Formula
The 555 timer astable formula treats each half of the cycle on its own. The high time uses both resistors, because C charges through R1 and R2 in series. Resistance is in ohms, capacitance is in farads and time is in seconds.
The low time uses R2 only, because C drains through R2 into pin 7. The 0.693 constant is the natural log of 2. It appears because C swings between one third and two thirds of the supply.
The two times add up to the period. The 555 timer frequency formula is one divided by that period, and TI rounds the constant to 1.44 in its data sheet. Ohms and farads in the formula give hertz.
Duty cycle is the share of each cycle that pin 3 spends high. In the standard circuit it depends on the two resistors alone, so a change in C moves the frequency and leaves the duty cycle where it was.
Take R1 = 4.7 kΩ, R2 = 68 kΩ and C = 10 µF. The high time is 503.9 ms and the low time is 471.3 ms, so the period is 975.3 ms. The 555 timer astable oscillator circuit runs at 1.025 Hz, or 61.52 pulses per minute. Its duty cycle is 51.67% and its mark to space ratio is 1.069 to 1.
The duty card also shows the low share, which is 48.33% in this example. That figure is the on-time of a load wired from the supply to pin 3, such as an LED that the output sinks. TI calls it the output driver duty cycle.
R1 and R2 From a Target Frequency
Most builds of a 555 timer astable oscillator circuit start from a frequency and a duty cycle, and the resistors are the unknowns. Set Solve For to R1 and R2 From Frequency, then enter the capacitor on hand. In the two equations below, T is one divided by the frequency and D is the duty cycle as a fraction.
A 2 kHz target at 60% duty with a 22 nF capacitor needs exactly 6.558 kΩ and 13.12 kΩ. Neither value is a standard part. The calculator tests the E24 values on each side and keeps the pair that lands closest, which is 6.8 kΩ and 13 kΩ. Those parts build 1.999 kHz at 60.37% duty.
The resistor tolerance setting picks the series. A ±1% setting searches E96 values, ±5% searches E24 and ±10% searches E12. The Resistors for Other Capacitors table repeats the design for each decade of capacitance and flags the rows where a resistor falls outside the limits of the selected timer IC.
In frequency mode the same table becomes Frequency With Other Capacitors. Each tenfold step in C divides the frequency by ten. With 4.7 kΩ and 68 kΩ, a 10 µF capacitor gives 1.025 Hz, 100 nF gives 102.5 Hz and 1 nF gives 10.25 kHz.
Duty Cycle Below 50% With a Diode
The standard 555 timer astable oscillator circuit cannot reach 50% duty, because the high time always includes R2. Equal resistors give 66.67%. Even R1 = 1 kΩ with R2 = 100 kΩ only comes down to 50.25%.
A signal diode across R2 removes that limit. Its anode goes to pin 7 and its cathode to pin 6, so C charges through R1 and the diode and still drains through R2. Many guides then give the high time as 0.693 × R1 × C, which assumes the diode drops no voltage.
A real diode does drop voltage, so C charges toward the supply minus that drop. Set Circuit Type to With Diode and the calculator uses the full charging equation for the high time.
VCC is the supply voltage and VD is the diode forward drop. With no drop the log term is 0.693, the textbook figure. With a 0.7 V drop the multiplier grows as the supply falls, because the drop is a bigger share of a smaller supply.
| Supply Voltage | Multiplier on R1 × C | High Time Against 0.693 |
|---|---|---|
| 5 V | 1.002 | 45% longer |
| 9 V | 0.835 | 20% longer |
| 12 V | 0.794 | 15% longer |
| 15 V | 0.771 | 11% longer |
Take a 1 kHz target at 25% duty with a 100 nF capacitor. The textbook formula asks for R1 = 3.607 kΩ and R2 = 10.82 kΩ. On a 5 V supply with a 0.7 V diode, those values run at about 900 Hz and 32.5% duty.
With the drop entered, the calculator asks for R1 = 2.495 kΩ instead. The E24 pair of 2.4 kΩ and 11 kΩ then builds 997.0 Hz at 23.98% duty. That answer holds at 5 V only, so set the supply voltage before reading off the resistors.
Why a Built 555 Misses the Formula
A common forum complaint is a 555 timer astable oscillator circuit that measures well away from its calculated frequency. The chip is rarely the cause. TI lists a typical astable drift of 150 ppm per °C, which is small next to ordinary part tolerance.
Frequency depends on resistance times capacitance, so the two tolerances stack. With ±5% resistors and a ±20% electrolytic, the worst case runs from 20.6% low to 31.6% high. The 1.025 Hz example can land anywhere from 0.814 Hz to 1.349 Hz.
Tighter parts close the gap. Resistors at ±1% with a ±5% film capacitor hold the spread to 5.7% low and 6.3% high. Duty cycle hardly moves, 51.5% to 51.8% in the example, because C cancels out of the duty ratio and only the resistors matter.
555 Astable Circuit With Potentiometer
A potentiometer in the R2 position makes a 555 timer astable oscillator circuit adjustable, and it is the usual way to trim out capacitor tolerance. Keep a fixed resistor in series with it so R2 never reaches zero. In the calculator, R2 is that fixed resistor and the Pot in Series With R2 field holds the pot value.
The Potentiometer Sweep on R2 table then lists the frequency and duty cycle at five positions of the pot. Take a 555 timer astable circuit with potentiometer built from R1 = 1 kΩ, R2 = 1 kΩ, a 100 kΩ pot and C = 100 nF. Its sweep runs as shown in the table.
| Pot Turned | R2 Total | Frequency | Duty |
|---|---|---|---|
| 0% | 1 kΩ | 4.809 kHz | 66.7% |
| 25% | 26 kΩ | 272.2 Hz | 50.9% |
| 50% | 51 kΩ | 140.1 Hz | 50.5% |
| 75% | 76 kΩ | 94.29 Hz | 50.3% |
| 100% | 101 kΩ | 71.07 Hz | 50.2% |
The sweep is not even across the rotation of a linear pot. Frequency follows one over R1 plus twice R2, so the first quarter turn drops the output from 4.809 kHz to 272.2 Hz. The other three quarters only take it down to 71.07 Hz.
555 Timer Astable Oscillator Circuit Diagram
The Wiring Diagram With Pin Numbers panel redraws the 555 timer astable multivibrator circuit diagram with the current R1, R2 and C values. It adds the diode when that circuit type is selected. For an astable 555 timer circuit on a breadboard, the eight pins connect as shown in the table.
| Pin | Name | Connection |
|---|---|---|
| 1 | GND | Ground rail |
| 2 | TRIG | Pin 6 and the top of C |
| 3 | OUT | The load, such as an LED with its series resistor |
| 4 | RESET | Supply rail |
| 5 | CONT | 10 nF capacitor to ground |
| 6 | THRES | Pin 2, the top of C and the lower end of R2 |
| 7 | DISCH | Junction of R1 and R2 |
| 8 | VCC | Supply rail, 4.5 V to 16 V for the NE555 or 2 V to 15 V for the TLC555 |
TI says to connect RESET to the supply when it is not used, and notes that a 0.01 µF capacitor from CONT to ground can improve operation. It also recommends a 0.1 µF ceramic bypass capacitor from pin 8 to ground.
Neither of those capacitors is the C in the timing formula. C is only the capacitor on pins 6 and 2. A larger value there slows the oscillator, and the 10 nF part on pin 5 is not part of the timing math.
Limits From the 555 Timer Datasheet
The fourth result card checks the 555 timer astable oscillator circuit against the chip picked under Timer IC. The choices are TI's bipolar NE555 and its CMOS TLC555. A green card means the design sits inside the figures below. An amber or red card names the limit that failed, and the note under the cards says what to change.
| TI Figure | NE555 | TLC555 |
|---|---|---|
| Supply voltage | 4.5 V to 16 V | 2 V to 15 V |
| Top astable frequency | 100 kHz | 2.1 MHz typical |
| Threshold pin current | Up to 250 nA | 10 pA typical |
| Maximum R1 + R2 | About 3.4 MΩ at 5 V and 10 MΩ at 15 V | No ceiling in the check |
| Pin 7 sink current | R1 kept at 1 kΩ or more | 150 mA absolute maximum |
| Output current | Up to 200 mA, sink or source | 100 mA sink and 10 mA source, typical |
TI ties the NE555 ceiling on R1 + R2 to the threshold pin current. Between 5 V and 15 V the calculator estimates that ceiling on a straight line, which gives 6.040 MΩ at 9 V. The TLC555 draws about 10 pA at the same pin, so megohm resistors with a small film capacitor are practical on the CMOS chip.
Pin 7 Peak Sink Current is the load on the discharge pin at the instant the output goes low. Pin 7 carries the current through R1 plus C draining through R2. At 9 V with 4.7 kΩ and 68 kΩ that is 2.003 mA. With the TLC555 selected, the card compares the peak with TI's 150 mA absolute maximum.
A 3.3 V build passes with the TLC555 selected and fails with the NE555. The TLC555C version starts at 2 V and the wider-temperature TLC555I starts at 3 V. TI gives the 0.693 formulas for frequencies below 100 kHz on this chip. Above that the card turns amber, because switching delays add to each cycle and the built circuit runs slower than the result.
What Pin 3 Can Drive
TI rates the NE555 output to sink or source up to 200 mA, so an LED and its series resistor can connect straight to pin 3. The high level sits below the supply under load. At 5 V and 100 mA, TI lists a typical high level of 3.3 V.
The TLC555 output swings closer to the supply rails, and it sources far less current. TI lists 10 mA typical for source and 100 mA typical for sink. A heavier load on a TLC555 belongs between the supply and pin 3, where the output sinks it.
Pin 3 of a 555 timer astable oscillator circuit gives a rectangular wave. For a cleaner tone, pass the output through a filter centered on the same frequency, sized with the Bandpass Filter Calculator. If the filtered tone needs more level, the Op Amp Gain Calculator sets the gain resistors.
The capacitor voltage at pins 6 and 2 rises and falls between one third and two thirds of the supply. Any load on that node changes the timing. To use that waveform elsewhere, buffer it with a high-impedance stage, and the Non-Inverting Op-Amp Resistor Calculator covers the resistor values.
555 Timer Calculator Questions
Why is the duty cycle 66% when R1 equals R2?
In a 555 timer astable oscillator circuit, C charges through both resistors and drains through one. With R1 = R2 = 10 kΩ and C = 100 nF, the high time is 1.386 ms and the low time is 693.1 µs. The high time is two thirds of the 2.079 ms period, so the duty cycle is 66.67% at 480.9 Hz.
The duty cycle falls toward 50% as R2 grows against R1, and it never gets there in the standard circuit. R1 = 1 kΩ with R2 = 100 kΩ gives 50.25%. Anything at or under 50% needs the diode across R2.
Does supply voltage change the 555 frequency?
In the standard 555 timer astable oscillator circuit it barely does. Both thresholds are fractions of the supply, so the charge and discharge times stay the same as the supply moves. TI lists a typical astable shift of 0.3% per volt.
The diode circuit is different, because the diode drop does not scale with the supply. Take a build with R1 = 3.607 kΩ, R2 = 10.82 kΩ, 100 nF and a 0.7 V diode. It runs at 899.7 Hz on a 5 V supply and 964.9 Hz on a 12 V supply.
How slow can a 555 astable oscillator run?
TI describes the 555 as working below 1 mHz, and the formula allows it. R1 = 100 kΩ, R2 = 1 MΩ and C = 1000 µF give a period of 24.26 minutes on paper. Capacitor leakage can stop a build that slow.
Nichicon specifies leakage for many aluminum electrolytic series at up to 0.01CV or 3 µA at rated voltage. With the ±20% electrolytic tolerance selected, the limits card applies that 0.01CV figure at the supply voltage.
At 9 V the example has only 2.727 µA charging C near the upper threshold, against 90 µA of allowed leakage. The card turns amber and reads Capacitor Leakage May Stall It. If the leakage exceeds the charging current, C never reaches two thirds of the supply and the output stays high.
The more dependable route to long periods is a faster 555 timer astable oscillator circuit with a film capacitor. A counter IC then divides its output down to the period that is needed.