A voltage divider splits an input voltage across two series resistors, producing an output set by their ratio — the same math this Voltage Divider Calculator applies to any resistor pair and supply voltage.
How the Output Voltage Is Produced
A resistive voltage divider scales an input voltage $V_{in}$ across two series resistors $R_1$ and $R_2$ according to Ohm’s Law. The output voltage measured at the node between the resistors is
$$V_{out} = V_{in} \cdot \frac{R_2}{R_1 + R_2}$$
The fraction $R_2/(R_1+R_2)$ is the voltage ratio. It depends only on the relative sizes of the two resistors, not on their absolute values. The total series resistance $R_{total}=R_1+R_2$ sets the quiescent current $I_q=V_{in}/R_{total}$ that flows continuously through the divider, which in turn determines the power dissipated in each resistor: $P_{R1}=I_q^2 R_1$ and $P_{R2}=I_q^2 R_2$.
The Thevenin equivalent resistance seen looking back into the divider from the output node is the parallel combination
$$R_{th} = \frac{R_1 \cdot R_2}{R_1 + R_2}$$
This $R_{th}$ governs how the divider behaves when loaded. It determines the short-circuit current $I_{sc}=V_{in}/R_1$, the thermal noise density $\sqrt{4kTR_{th}}$ (evaluated at 25 °C using $k=1.38\times10^{-23}$ J/K), and the RC time constant $\tau = R_{th} \cdot C_{load}$ when driving a capacitive load such as an ADC input pin. The $-3$ dB bandwidth is $f_{3dB}=1/(2\pi\tau)$, and the time to settle within 1% of final value is $t_{settle}=4.605\tau$.
Worked Example: 10 V into a 10 kΩ / 10 kΩ Divider
Start with $V_{in}=10$ V, $R_1=10$ kΩ, and $R_2=10$ kΩ. The total resistance is $10{,}000 + 10{,}000 = 20{,}000$ Ω. The voltage ratio is $10{,}000/20{,}000 = 0.5$, so $V_{out}=10 \cdot 0.5 = 5.00$ V.
The Thevenin resistance is $(10{,}000 \times 10{,}000)/20{,}000 = 5{,}000$ Ω. The quiescent current is $10/20{,}000 = 500$ µA, which means $P_{R1}=(500\times10^{-6})^2 \times 10{,}000 = 2.5$ mW and the same for $P_{R2}$. The short-circuit current is $10/10{,}000 = 1$ mA. For a load to introduce less than 1% error, it must be at least $99 \times 5{,}000 = 495$ kΩ.
With a 10 pF ADC pin capacitance, $\tau = 5{,}000 \times 10\times10^{-12} = 50$ ns. The $-3$ dB bandwidth is $1/(2\pi \times 50\times10^{-9}) \approx 3.18$ MHz, and the 1% settling time is $4.605 \times 50 \approx 230$ ns. The noise density at 25 °C is about $9.07$ nV/$\sqrt{\text{Hz}}$.
When the Divider Is Stiff Enough for an ADC
The calculator reports a 1% load threshold: $R_{load} \geq 99 \cdot R_{th}$. If your ADC or op-amp input impedance falls below this value, the loaded output will droop measurably from the open-circuit prediction. Many microcontroller ADCs present an input impedance in the hundreds of kilohms to megohms, but some sensor front-ends or bipolar transistor loads can be far lower.
Power dissipation scales with the square of current. At 10 V across 20 kΩ total, the example above wastes 5 mW. Drop the resistors to 1 kΩ each and quiescent current rises to 5 mA, burning 25 mW per resistor. That may be trivial on a mains supply, but on a coin-cell sensor node it can dominate battery life.
Noise density improves as $\sqrt{R_{th}}$, so lower resistances yield quieter dividers — a 5 kΩ Thevenin resistance produces roughly 9 nV/$\sqrt{\text{Hz}}$, while a 500 kΩ divider produces about 90 nV/$\sqrt{\text{Hz}}$.
What Moves the Numbers Most
The ratio $R_2/R_{total}$ fixes $V_{out}$. Doubling $R_2$ while holding $R_1$ constant raises the output; halving it lowers the output proportionally. Absolute resistance values, however, control power, noise, and speed. Increasing both resistors by a factor of ten leaves $V_{out}$ unchanged but multiplies $R_{th}$ by ten, which multiplies $\tau$ by ten and divides $f_{3dB}$ by ten.
The 10 pF load capacitance built into the bandwidth calculation is a representative ADC pin capacitance. Real layouts add parasitic capacitance from traces and vias.
A divider with $R_{th}=1$ MΩ and 10 pF has $\tau=10$ µs and $f_{3dB}\approx 15.9$ kHz — fine for a temperature sensor, inadequate for a high-speed sampling front end. Resistor tolerances also matter: two 5% resistors can produce a ratio error up to roughly 10% in the worst case.
Common Questions
What is the voltage divider formula?
$V_{out}=V_{in}\cdot R_2/(R_1+R_2)$. The output is the input multiplied by the fraction of total resistance that appears below the tap point.
How do I pick resistor values for a voltage divider?
Choose the ratio to get the desired $V_{out}$, then set the absolute magnitude to balance power draw, noise, and load tolerance. Lower resistances waste more power but produce stiffer outputs and less thermal noise. Higher resistances save power at the cost of slower settling and greater sensitivity to loading.
What does Thevenin equivalent resistance mean in practice?
$R_{th}=R_1\parallel R_2$ is the effective resistance the load sees. It sets the output impedance of the divider. A 100 kΩ $R_{th}$ driving a 1 MΩ ADC input introduces about 9% error; a 5 kΩ $R_{th}$ introduces negligible error.
Why does my ADC read lower than the calculated divider output?
The ADC input impedance forms a second divider with $R_{th}$. If the ADC data sheet lists 100 kΩ input impedance and your divider has $R_{th}=50$ kΩ, the loaded output drops to roughly two-thirds of the open-circuit value. The calculator’s 1% load threshold flags when this effect becomes significant.
How much power does a voltage divider dissipate?
Total power is $V_{in}^2/(R_1+R_2)$. It splits between the two resistors in proportion to their values. A 12 V supply across two 100 kΩ resistors draws 60 µA and dissipates 720 µW total; the same supply across two 1 kΩ resistors draws 6 mA and dissipates 72 mW.
Can a voltage divider be used to step down mains voltage?
Not safely for power delivery. Dividers waste the same fraction of energy that they drop, and they provide no isolation. For high-voltage measurement, use an isolated probe or a dedicated attenuator designed for safety clearance and power rating.
What limits the speed of a voltage divider?
The RC time constant $\tau=R_{th}\cdot C_{load}$ sets the bandwidth and settling time. The calculator assumes 10 pF, typical of an ADC pin. Long traces, coaxial cables, or op-amp input capacitance can raise $C_{load}$ by orders of magnitude and slow the response accordingly.
What This Analysis Does and Does Not Cover
The results assume ideal resistors at 25 °C with no parasitic inductance or capacitance beyond the fixed 10 pF load model. Real resistors have tolerance bands, temperature coefficients, and voltage coefficients that shift the actual ratio. The calculator does not account for these effects, nor for leakage currents, PCB trace resistance, or non-linear loads. Use the output as a design starting point; verify against the resistor data sheet and the actual load conditions in your circuit.